This application claims the priority benefit of Taiwan application serial no. 88107586, filed May 11, 1999, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
This invention relates to integrated circuit (IC) memory testing methodology, and more particularly, to a method of performing a BIST (built-in self test) procedure on embedded memory through a time-division multipexed scheme with a reduced number of probing pads.
2. Description of Related Art
Due to advances in IC fabrication technology, it is today a typical practice to integrate both a data processing unit and a memory unit on the same chip. Such a memory unit is customarily referred to as embedded memory. As embedded memory is increased in capacity, however, it would cause problems in operation to the associated ASIC (Application-Specific Integrated Circuit) and logic circuits. Moreover, it would be difficult for memory testers to test high-capacity embedded memory units since most existing memory testers are old-fashioned with a low-speed clock rate that can be hardly used for the testing of high-speed memory devices.
For low-capacity embedded memory units, it would be sufficient to perform testing on them in a cost-effective manner without having to use BIST or gang probing techniques. However, system-on-chip is a major trend in IC design and fabrication, and the embedded memory should be high in speed and large in capacity and word length. Conventionally, BIST method is used for the testing of embedded memory. However, BIST method lacks repair capability so that bad memory cells can not be automatically repaired. Today""s embedded memory has now reached a capacity in the range from 16 MB to 32 MB. Typically, embedded memory chips with built-in repair capability is about 5% to 30% larger in size than those with BIST but no repair capability since more layout area is required to incorporate the repair capability. One type of embedded memory utilizes probing method to detect and repair bad memory cells. One drawback to this method, however, is that it would be unsuitable for use on embedded memory with a large word length. Moreover, it would require a large layout area on the chip to incorporate the required probing pads.
FIG. 1 is a schematic block diagram of a conventional BIST circuit used to test an embedded memory unit 60. The BIST circuit includes an ATPG_A (Automatic Test Pattern Generator for Address) unit 30 and an ATPG_D (Automatic Test Pattern Generator for Data) unit 40. The test procedure performed by the BIST circuit is shown in FIG. 2. When the BIST-EN (BIST-enable) pad 10 receives an enable signal, it activates the BIST logic unit 20 to issue a request for a write cycle, which causes the ATPG_A unit 30 to generate an address signal and the ATPG_D unit 40 to generate a block of test data. The data generated by the ATPG_D unit 40 are then stored in the storage area 64 of the embedded memory unit 60 at the address specified by the ATPG_A unit 30. The read/write operation on the embedded memory unit 60 is controlled by the ASIC device 50. During a read cycle, the memory I/O unit 66 retrieves the test data that were previously stored into the storage area 64 of the embedded memory unit 60 at the address specified by the ATPG_A unit 30. The retrieved data are then forwarded to the comparator 70, where the retrieved data are compared in a bit-by-bit manner with the originally-generated test data from the ATPG_D unit 40. If all bits are OK, the comparator 70 generates a first logic signal, for example 0, indicative of such a condition; otherwise, the comparator 70 generates a second logic signal, for example 1, which causes the OR gate 80 to perform an OR-operation on the test data. If the OR gate 80 outputs 0, it indicates that all the memory cells are all correct; otherwise, if 1, it indicates that at least one memory cell in the embedded memory unit 60 is bad.
The output of the OR gate 80 is then outputted via the PASS/FAIL pad 90 to external circuitry (not shown). The condition of the output being 0 indicates PASS; whereas the condition of the output being 1 indicates FAIL. If a FAIL signal is received, the entire embedded memory unit 60 will be discarded.
A conventional method for repairing bad memory cell is to provide a bit-mapping memory tester to the embedded memory unit, which includes a cache memory unit with the same capacity as the embedded memory unit, and is capable of repairing a bad memory cell by mapping the address of the bad memory cell to the cache memory. One draw-back to this solution, however, is that when the embedded memory is quite large in capacity, it would make the use of cache memory quite costly to implement. Moreover, when word length is large, it will require a large number of probing pads on the memory chip, and thus a large layout area to incorporate these probing pads, which makes it quite costly to implement.
It is therefore an objective of this invention to provide a new method for performing a self-test on an IC memory device, which utilizes a time-division multipexed scheme to detect bad memory cells in a more efficient manner.
It is another objective of this invention to provide a method for performing a self-test on an IC memory device, which can help reduce the number of required probing pads on the memory chip to save cost.
In accordance with the foregoing and other objectives of this invention, a new method is provided for performing a BIST procedure on embedded memory. The method of the invention includes the following procedural steps: (1) generating a block of test data; (2) performing a write operation to write the test data into a specified address in the embedded memory; (3) performing a read operation to retrieve the test data from the embedded memory; (4) comparing the retrieved test data with the originally-generated test data; and (5) if any bit is mismatched, outputting a sequence of blocks of error bits indicative of the bad memory cells in the embedded memory, if any; the length of each error-bit block being an integer division of the word length of the embedded memory, and the sequence of error-bit blocks being transferred in a time-division multipexed scheme via a plurality of probing pads equal in number to the length of the error-bit block.
The foregoing method is characterized in the use of a time-division multipexed scheme to obtain the addresses of bad memory cells so that these address data can be used to indicate the locations of the bad memory cells during repair process. Moreover, the invention is characterized in that it requires only a fewer number of probing pads than the prior art so that the required layout area for the BIST procedure can be reduced as compared to the prior art. The invention is therefore more cost-effective to implement than the prior art.